The Bottleneck Nobody Saw Coming
When industry analysts discuss constraints on AI chip supply, they typically focus on wafer fabrication capacity at leading-edge nodes. But in 2026, the most critical bottleneck is no longer the fab — it is the packaging line. TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology has become the single most constrained resource in the AI semiconductor supply chain, limiting how many AI accelerators can ship regardless of how many wafers TSMC can produce.
CoWoS is the 2.5D packaging technology that enables the integration of multiple compute chiplets with High Bandwidth Memory (HBM) stacks on a single silicon interposer. Every major AI accelerator — Nvidia's Blackwell and Rubin, AMD's MI300 and MI400, Google's TPU, Amazon's Trainium — depends on CoWoS or equivalent advanced packaging. Without it, the most powerful AI chips in the world are just individual dies that cannot be assembled into functional systems.
Quantifying the Capacity Gap
The numbers tell a stark story. TSMC's CoWoS capacity evolution shows a relentless demand curve outstripping supply: 75,000 wafer equivalents per month in 2023, 95,000 in 2024, approximately 115,000 by mid-2025, and a target of 150,000+ by end of 2026. Yet customer demand projections through 2026 suggest requirements exceeding 180,000 units monthly, implying a persistent shortfall of 30% or more even as TSMC aggressively expands capacity.
Nvidia alone reportedly secures over 60% of available CoWoS capacity. This allocation dominance means every other AI chip maker — AMD, hyperscaler ASIC teams, and AI startups — competes for the remaining capacity. The situation has forced TSMC to ration supply, with allocation decisions effectively determining which AI chips reach the market and which are delayed.
Why Packaging Is Harder to Scale Than Fabs
Conventional wisdom suggests that advanced packaging should be simpler to scale than leading-edge wafer fabs. In practice, the opposite is true for CoWoS. Several factors constrain packaging capacity expansion.
Equipment availability is the primary bottleneck. Advanced packaging requires specialized tools — silicon interposer manufacturing equipment, hybrid bonding tools, through-silicon via (TSV) etchers — with a very limited supplier base. Lead times for critical equipment exceed 18 months.
Substrate supply is another constraint. The silicon interposers used in CoWoS require defect-free large-area silicon, which has its own manufacturing challenges. The ABF (Ajinomoto Build-up Film) substrates used in the final packaging step are also in short supply.
Qualification cycles add further delays. Each customer chip design requires months of qualification before it can be certified for production on a given packaging line. This means new capacity cannot be instantly utilized even when it comes online.
Outsourcing to OSAT Partners
Recognizing these constraints, TSMC is expanding outsourced CoWoS production in the second half of 2026. The focus is on the CoW stage (Chip-on-Wafer) within 2.5D packaging, which is viewed as the most mature and high-throughput integration step.
Key OSAT partners include ASE Technology Holding and its subsidiary SPIL, as well as Amkor Technology. These third-party packaging and testing contractors are essential to expanding the overall capacity envelope. ASE has kicked off its largest-ever fab construction program in 2026, with six new facilities slated to break ground worldwide. The company's new Kaohsiung facility, with total investment exceeding TWD 108.3 billion, will focus on advanced semiconductor testing for AI, HPC, 5G, and automotive applications.
ASE CEO Tien Wu has described 2026 as the company's most aggressive year for fab construction, with expansion projects spanning the United States, Malaysia, Japan, and Germany. ASE initially budgeted $7 billion for 2026 capex but has indicated potential upward revision due to robust market demand.
Amkor's Arizona and Vietnam Expansion
Amkor Technology is pursuing a parallel expansion strategy. The company is building a state-of-the-art advanced packaging and test campus in Peoria, Arizona, on a 104-acre site. It has now secured an additional 67-acre adjacent parcel for future expansion. This campus is expected to be the first high-volume advanced packaging OSAT facility in the United States, supporting demand across AI, HPC, automotive, and communications markets.
Meanwhile, Amkor is accelerating its Vietnam operations. Since 2021, the company has invested a cumulative $1.6 billion to build advanced packaging facilities in Bac Ninh Province. The Vietnam site benefits from competitive labor costs, strategic location, and an established industrial base.
Samsung is also entering the fray, with plans to invest $4 billion in a new semiconductor packaging and testing facility in Thai Nguyen Province, northern Vietnam. This would mark Samsung's largest single investment in the segment since entering Vietnam in 2008.
TSMC's In-House Expansion
Despite outsourcing, TSMC continues to build its own packaging capacity aggressively. The company acquired Innolux's 5.5G fab in Tainan for NT$17.1 billion, which could accommodate up to an additional 30kwpm of CoW capacity. Current expansion is concentrated at the AP6 facility in Zhunan, with AP5 in Taichung contributing capacity from late 2024. Construction at AP7 Phase 1 in Chaiyi is expected to be completed in 2026, with production commencing in late 2027 and 2028.
J.P. Morgan estimates that TSMC's CoWoS capacity will reach 105,000 wafers per month by end of 2026, up from earlier estimates. UBS projects further expansion to 150,000 wpm, reflecting the upward revision of demand forecasts driven by continued hyperscaler investment in AI infrastructure.
The Competitive Landscape
The CoWoS bottleneck has created strategic dynamics across the industry. TSMC's dominance in CoWoS gives it significant leverage over customers and competitors alike. Samsung is developing its own equivalent packaging technology, I-Cube and X-Cube, to offer a differentiated value proposition to customers seeking to diversify their supply chain. Intel's EMIB (Embedded Multi-die Interconnect Bridge) and Foveros 3D packaging technologies are also positioning the company as an alternative for customers looking to reduce dependence on TSMC.
The packaging bottleneck is likely to persist through at least 2027, even with all the expansion plans currently in motion. Equipment lead times, substrate constraints, and qualification cycles are structural factors that cannot be shortcut. For the AI industry, this means that packaging capacity — not wafer fab capacity — will continue to be the binding constraint on AI compute availability.